1. Field of the Invention
The invention relates to semiconductor devices and a method of manufacturing thereof, and more particularly, relates to semiconductor devices including those such as self-aligned bipolar transistors and field effect transistors (FETs), and a method of manufacturing thereof.
2. Description of the Related Art
Recently, in such a field of computers, higher speed information processing has been required. Accordingly, semiconductor integrated circuit devices used in the field are also required to have a higher speed.
Bipolar transistors are used as high speed semiconductor devices, e.g., in computers. An advanced, self-aligned bipolar transistor, which is expected to have high speed information processing, is disclosed in JP-A-62-183558. This bipolar transistor is made as follows:
Referring to FIG. 1, collector contact n -type regions 5 are selectively formed in a p-type semiconductor substrate 1, on the surface of which a buried n.sup.+ -type layer 2 and an epitaxial layer 3 have been formed, to thereby contact the buried layer 2. Insulating regions 8 for isolation are then selectively formed in given areas of the substrate 1.
Subsequently, a lower insulating film 9, a polysilicon film 10 doped with p-type impurities for base electrodes, and an upper insulating film 11 are formed in order, after which holes 12 are formed that go through said three layers of film and reach the epitaxial layer 3 adjacent to the collector contact regions 5.
Polysilicon films 45 for forming the base electrode are then selectively formed on the sides of the hole 12. By the subsequent heat treatment, p-type impurities are doped from the polysilicon film 10 having been doped with the p-type impurities into the epitaxial layer 3 through the polysilicon film 45 on the side of the hole 12, to thereby form a doughnut-like external base region 13. P-type impurities are then ion-implanted inside the doughnut-like external base region 13 to thereby form an internal base region 14.
Subsequently, side walls 15 of insulation film covering the polysilicon film 45 are formed on the sides of the hole 12, to thus newly form a hole 16 inside the old hole 12. A polysilicon film doped with n-type impurities is then formed, covering the hole 16, and patterned, to thereby form an emitter electrode 17. By the subsequent heat treatment, n-type impurities are doped from the hole 16, to thereby form an emitter region 18 inside the internal base region 14.
A contact hole 19 is formed in the insulating films on the collector contact region 5, and a via-hole 44 in the insulating film on the base electrode 10. Metallic emitter, base, and collector electrodes 20, 21, and 22 are then formed by aluminum, to thus complete a self-aligned bipolar transistor.
To achieve a higher speed in such a bipolar transistor, it is necessary to form the device in such a manner that the areas of a base region, consisting of external and internal base regions 13 and 14, and an emitter region 18 are as small as possible, to thereby reduce the parasitic capacitances of a base/collector junction and a base/emitter junction.
It is also necessary to form a thin internal base region 14 in order to provide high speed prior bipolar transistors. However, when the internal base region 14 is thin, the base resistance just under the unit is high, and the so-called emitter crowding effect occurs, in which the collector current passes only at the peripheral portion of the emitter region 18 and does not pass inside the region 18, because the inside region has a higher base resistance than that of the outside region. Although the inside of the emitter region 18 scarcely participates the operation of the transistor, the parasitic capacitance preventing high speed operation remains. On the other hand, a parasitic capacitance between a base and a collector or a base and an emitter prevents high speed operation of a high speed bipolar transistor because of the charge and discharge of the parasitic capacitance. Thus, the internal base region does not participate the operation of the bipolar transistor, and the junction parasitic capacitance in the internal base region prevents the high speed operation of the bipolar transistor, and accordingly, it is preferred that the portion of the internal base region does not exist. Namely, to produce a high speed bipolar transistor, it is preferred that a base is formed only in a region adjacent to an emitter, the region being close to a base electrode, i.e., having a low base resistance.
In the above method of manufacturing, although the internal base region 14 is formed by ion implantation, the shallower implantation of conductive impurities is very difficult because of channeling. The formation of a shallow internal base region 14 has therefore limitations.